1. Field of the Invention
The present invention relates to a method of forming fine patterns in a semiconductor device, and more particularly, to a method of forming fine patterns which can prevent distal ends of the lines (i.e, line edges) of the fine pattern from being rounded off.
2. Description of the Related Art
The various patterns in a semiconductor device are formed by a sequence or series of various photolithography techniques. The photolithography techniques generally include steps of: (a) forming a photo resist layer on an insulating or conductive layer; (b) irradiating the photo resist layer with X-ray or ultraviolet light through a pre-defined pattern to alter the solubility thereof; (c) forming a photo resist pattern by removing portions having a higher solubility by developing the exposed photo resist layer after exposing predetermined portions of the photo resist layer to the designated light source; and (d) and forming various patterns such as electrical wirings or electrodes by etching the exposed portions of the layer where the pattern is formed.
FIGS. 1A and 1B are plan views illustrating a method of forming patterns in a semiconductor device according to a conventional lithography process. FIG. 1A is a plan view partially showing the photo mask for forming an island type rectangular pattern on a semiconductor substrate. A light masking (or shielding) layer pattern 12 is formed on a transparent mask substrate 10, with the light masking layer pattern 12 having a rectangular shaped island type pattern.
With the conventional method of forming a pattern, a photo resist pattern is formed by exposing the photo mask to light to change the solubility of the photo resist layer, and then developing this photo resist layer that is coated on a wafer (i.e., a semiconductor substrate) to create the pattern. However, during the exposure process, the line edges or distal ends 12a of the light masking layer pattern experience a three-dimensional optical diffraction phenomenon. As shown in FIG. 1B, the 3-D optical diffraction causes the line edges or distal ends 12a to be rounded, such that the rectangular photo resist pattern 22 fails to form the desired rectangular pattern on the semiconductor substrate 20.
This 3-D phenomenon is called the optical proximity effect, and periodic grain type patterns, such line/space patterns (xe2x80x9cL/S patternsxe2x80x9d) are only affected slightly by the optical proximity effect. However, the operation of island patterns, such as a capacitor electrode of dynamic random access memory (DRAM) or a gate electrode of static random access memory (SRAM), are seriously affected by the rounding of the distal ends or line edges of the pattern due to the optical proximity effect.
In particular, the rounding becomes more serious as the design rule decreases since the size of the pattern is reduced and the processing margin greatly decreases. For example, in case of a gate electrode of a SRAM device, the rounding of the line edges is about 70 nm when the extension is about 100 nm with respect to an active region of an underlying layer. Therefore, the processing margin deteriorates and leakage current increases since the overlap margin is only about 30 nm, which is insufficient for the active region of the gate electrode.
In an effort to prevent the rounding of line edges of the pattern, a phase shift mask (PSM) which shifts the phase of the incident light is utilized. Also, a feed type light proximity compensation method may be employed. In this method, a subsidiary pattern having a bar shape is formed at the portion of the light masking layer pattern of the photo mask where the rounding occurs.
In case of the phase shift mask, since the light passing through the phase shift layer has a phase opposed to that of the light passing over others regions of the phase shift mask, the contrast of the pattern image can be increased by utilizing the diffraction phenomenon of the light, but the rounding of the line edges of the pattern cannot be completely eliminated.
As for the feed type light proximity compensation method, the overlap margin can be increased slightly by enhancing the rounding of about 30 to 40 nm when it is applied to the pattern under a 0.15 xcexcm design rule, however, the improvement of the rounding may be limited in case where pattern has a 0.12 xcexcm design rule.
Therefore, several methods of forming the pattern through a double exposure process using two photo masks are used to try and improve the rounding of the line edges of the pattern.
FIGS. 2A to 2D are cross-sectional views and plan views illustrating a method of forming fine patterns in a semiconductor device by the conventional double exposing process disclosed in Korean Patent Laid-Open Publication No. 1999-015462 (Korean Patent Application No. 1997-037588).
FIG. 2A is a cross-sectional view of a photo resist layer 54 on a semiconductor substrate 50 having a layer 52 to be etched thereon for forming a pattern. FIG. 2B is a plan view of the photo resist layer 54 being exposed through a first photo mask having longitudinally extending patterns 54a formed thereon. FIG. 2C is a plan view of the photo resist layer 54 being exposed through a second photo mask having laterally extending patterns 54b formed thereon. FIG. 2D is a cross-sectional view taken along the line of 2xe2x80x942 in FIG. 2C showing the resulting photo resist pattern 54c formed by developing the photo resist pattern 54. Thereafter, the desired pattern is formed on the semiconductor substrate 50 after etching the layer to be etched 52 by using the photo resist pattern 54c as an etching mask.
While the conventional double exposing method can prevent the optical diffraction phenomenon, the rounding of the pattern is still generated during the double exposure process since the latent image is overlapped in the region where the first exposed pattern 54a and the second exposed pattern 54b intersect each other.
It is therefore a first objective of the present invention to provide a method of forming fine patterns in a semiconductor device, which can prevent the rounding of the line edges of the pattern.
It is a second objective of the present invention to provide a method of simultaneously forming fine patterns comprising a line/space pattern and an island type pattern in a semiconductor device, which can prevent the rounding of the line edges of fine pattern.
To accomplish the first objective of the present invention, one preferred embodiment of the present invention provides a method of forming fine patterns as follows. First, a layer to be etched for forming a main pattern is formed on a semiconductor substrate and then a hard mask layer is formed on the layer to be etched. A first hard mask layer pattern, defining a first peripheral portion of the main pattern in a first direction, is formed by patterning the hard mask layer. Then a second hard mask layer pattern, defining the first and a second peripheral portion of the main pattern in the first and second directions, is formed by patterning the first hard mask layer pattern, the second hard mask layer pattern being identical to the main pattern. Thereafter, the main pattern is formed by etching the layer to be etched using the second hard mask layer pattern.
The first hard mask layer pattern is formed by forming a first photo resist pattern on the hard mask layer to define the first peripheral portion of the main pattern in the first direction and by etching the hard mask layer by using the first photo resist pattern.
The second hard mask layer pattern is formed by forming a second photo resist pattern on the resultant structure, including the first hard mask layer pattern, to define the second peripheral portion of the main pattern in the second direction and by etching the first hard mask layer pattern by using the second photo resist pattern. Preferably, the hard mask layer is composed of a material having an etching selectivity higher than that of the layer to be etched during etching process.
Also, to accomplish the first objective of the present invention, another preferred embodiment of the present invention provides a method of forming fine patterns in a semiconductor device wherein a layer to be etched is formed on a semiconductor substrate for forming a main pattern. Then, a hard mask layer is formed on the layer to be etched and then a first photo resist layer is coated on the hard mask layer. A first photo resist pattern is formed through exposing and developing the first photo resist layer by using a first photo mask having a first light masking layer pattern extending in a first direction. A first hard mask layer pattern is formed by etching the hard mask layer using the first photo resist pattern. After removing the first photo resist pattern, a second photo resist layer is coated on the resultant structure including the first hard mask layer pattern. A second photo resist pattern is formed through exposing and developing the second photo resist layer by using a second photo mask having a second light masking layer pattern extending in a second direction perpendicular to the first direction. A second hard mask layer pattern identical to the main pattern is formed by etching the first hard mask layer pattern using the second photo resist pattern. After removing the photo resist pattern, the main pattern is formed by etching the layer to be etched using the second hard mask layer pattern.
To achieve the second objective of the present invention, still another preferred embodiment of the present invention provides a method of simultaneously forming fine patterns comprising a line/space pattern and an island type pattern in a semiconductor device. In this method, a layer to be etched is formed on a semiconductor substrate for forming a main fine pattern. A hard mask layer is formed on the layer to be etched and a first photo resist pattern is formed on the hard mask layer, the first photo resist pattern being patterned to form the line/space pattern in a first region where the line/space pattern is formed and extending along a first direction into a second region where the island pattern is formed. Then, a first hard mask layer pattern is formed by etching the hard mask layer using the first photo resist pattern. After removing the first photo resist pattern, a second photo resist pattern is formed on the resultant structure including the first hard mask layer pattern, the second photo resist pattern being patterned to form the line/space pattern in the first region and extending into the second region along a second direction perpendicular to the first direction. Thereafter, a second hard mask layer pattern identical to the main fine pattern is formed by etching the first hard mask layer pattern using the second photo resist pattern. After removing the second photo resist pattern, the main fine pattern is formed by etching the layer to be etched using the second hard mask layer pattern.
According to the present invention, after the first hard mask layer pattern is formed by primarily etching the hard mask layer through the first lithography process, the second hard mask layer pattern is formed by secondarily etching the hard mask layer through the second lithography process. Therefore, the portion of the pattern where the rounding is generated can be cut twice by the double lithography processes, however, the first and second latent images cannot be overlapped since the second photo resist pattern is formed after the first photo resist pattern is removed.